Due to the complex nature of microchip circuit design, clock signals often become skewed at one or more components within the circuit design such that data signals may arrive at a component before the respective clock signal arrives. When the data signal arrives too early with respect to a clock signal at a latch or flop device, a hold time violation occurs within the circuit. When a hold time violation occurs within an electrical circuit, the data transmitted on the data signal may not be latched or stored in the flop device correctly resulting in lost data signals and, ultimately, failure of the microchip design.
Hold time violations are often corrected in the design phase of the circuit by slowing down the data path or speeding up the clock signal. However, in the later stages of many circuit designs, changing the clock network is often not a viable option such that correction of hold time violations can be fixed through the addition of delay elements within the data signal path. In general, data signals may be delayed by inserting a buffer element or swapping devices along the data path with a different sized element to slow down the data signal. However, because these corrections often occur in the later stages of the circuit design, it is often desirous to minimize the number of alterations made to the design as any change in the design may have far-reaching impact on the design cost. In addition, the microchip design can also generally account for any setup time violations (i.e., the desired executing speed of the electrical circuit) such that the addition of too many delay elements into the circuit design may cause the execution speed of the circuit to fall below the maximum allowed time. Thus, what is needed is a method to efficiently select nodes of a microchip design to correct one or more hold time violation that minimizes the number of alterations and changes made to the design without breaking setup time constraints for the design.